A clock domain crossing occurs whenever data is transferred from a flop driven by one clock to a flop driven by another clock. Crossing the clock domains may cause metastability, data loss or other issues. To avoid metastability, a circuit design may include a multi-flop synchronizer to allow sufficient time for oscillations to settle down to ensure that a stable output is obtained in the destination domain. To avoid data loss, a circuit design for asynchronous domain crossings may include an asynchronous First-In First-Out (FIFO) while a circuit design for synchronous domain crossings may include a finite state machine (FSM).